Cadence Physical Verification System v15.13.000 | 2.9 GB
Cadence Design Systems, Inc., the leader in global electronic design innovation, has presented 15.13 version of Physical Verification System (PVS) is the premier signoff solution enabling in-design and back-end physical verification, constraint validation, and reliability checking.The system integrates with industry-standard Cadence Virtuoso custom/analog, Cadence Innovus digital design, and mixed-signal flows. This provides you with an end-to-end design and signoff physical verification solution integrated with all Cadence tools.
With PVS, you can complete advanced-node design signoff checks (DRC and LVS) with peace of mind. Foundries provide the PVS rule decks, and PVS provides efficient, comprehensive debug tools to reduce debug time and increase productivity. This solution supports advanced process node technologies (such as double patterning, triple patterning, quadruple patterning, 3D-IC, FinFET rules,advanced device extraction, and more), and it extends physical verification technology into design reliability checking and constraint validation. PVS also offers a distributed processing capability that greatly accelerates throughput without requiring specialized hardware.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Name: Cadence Physical Verification System (PVS)
Supported Architectures: x86_64 (lnx86)
System Requirements: Linux
Supported Operating Systems: RHEL 5.5, RHEL 6, SLES 11
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