Cadence Encounter Test 15.12.000 | 1.8 Gb
Cadence Design Systems, Inc., the leader in global electronic design innovation, has presented 15.12 version of Encounter Test, is a key technology of the Cadence Encounter digital IC design platform.
Cadence Encounter Test provides a comprehensive methodology for 3D-IC design-for-test and automatic test pattern generation that includes a DfT architecture that controls and observes an individual die from the chip I/Os, different test modes to control application of tests up and down the stack, and interconnect tests to detect through-silicon via defects.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Name: Cadence Encounter Test
Supported Architectures: X86_64
Website Home Page :
System Requirements: Linux / IBM RISC System/6000
Supported Operating Systems: RHEL 5, RHEL 6, SLES 11.0 / IBM RISC System/6000
Size: 1.8 Gb
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