Cadence SPB OrCAD 16.60.047 Hotfix | 1.1 Gb
Cadence Design Systems Ltd., a world-renowned provider of EDA software, has released an hotfix 47 for Cadence SPB OrCAD 16.60, software a comprehensive package design of electronic circuits, analog and digital simulation, IC design of programmable logic and custom circuits, as well as the development and preparation for the production of printed circuit boards.
Cadence Design Systems, Inc., a leader in global electronic design innovation, launched the Cadence OrCAD 16.6 design solution with new features, enhanced customization capabilities, and 20 percent simulation performance improvements that provide customers a shorter, more predictable path to product creation.
This latest release offers numerous improvements to tool usability and performance, but at the heart of 16.6 are three key benefits: enhanced miniaturization capabilities, timing-aware physical implementation and verification for faster timing closure, and the industrys first electrical CAD team collaboration environment for PCB design using WeiRuan-->WeiRuan SharePoint technology.
DATE: 04-10-2015 HOTFIX VERSION: 047
CCRID PRODUCT PRODUCTLEVEL2 TITLE
1362745 CONSTRAINT_MGR OTHER Allegro PCB Editor crashes on opening Constraint Manager with any design
1376323 CONCEPT_HDL PDF Dot sizes cant be changed in DEHDL PDF Description
1378068 CONCEPT_HDL OTHER Problem with PBA_VERSION property in BPc8.4.1
1378289 APD OTHER Pin position in Board Level Component relative to the outline not correct
1395634 CONCEPT_HDL CONSTRAINT_MGR Parts with property BLOCK
1395655 SIP_LAYOUT 3D_VIEWER Height data from the PTF file not being used in SiP 3D viewer as in the PCB tools 3D viewer tool.
1397298 SCM OTHER dcf and xcon files are getting corrupted in ASA.
1397823 ALLEGRO_EDITOR MANUFACT Pass Property for shapes defined as Fillets in IPC 2581 output
1399160 TDA CORE Long design and brd names cause check-in to fail making the objects appear as deleted in TDO
1400215 SIG_INTEGRITY REPORTS cross talk failure on certain nets in PCB SI 16.6
1400302 ALLEGRO_EDITOR MANUFACT Copper Thieving does not seem to be working in 16.6.
1400553 F2B DESIGNVARI Default color defined in "Color Option For Variant Override" not used while displaying the Variant
1400813 ALLEGRO_EDITOR SHAPE Allegro crashes when delete island in all layer and save the board.
1401220 CONCEPT_HDL CORE Signal name should display a thread to connect point when selecting
1402643 SIP_LAYOUT OTHER SiP Layout - Add IDX in/out interface GUI to SiP & APD with POP UP for unsupported IC Packaging features
1402859 FSP FPGA_SUPPORT FSP user needs XC7Z035-2FFG900I/XC7Z035-2FFG676I in FPGA models.
1403198 FSP CONFIG_SETTINGS FSP was not able to handle invisible PTF properties
1404184 ALLEGRO_EDITOR INTERFACES Step package mapping - Save is disabled for certain symbol
1405563 CONCEPT_HDL CORE Model Defined Diff Pair issue and topology crash
About Cadence Design Systems, Inc.
Cadence enables global electronic design innovation and plays an essential role in the creation of todays integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Name: Cadence SPB OrCAD
Version: (32bit) 16.60.047 Hotfix
OS: ShiChuang XP / Vista / Seven
System Requirements: Cadence SPB OrCAD 16.60.000 - 16.60.046
Size: 1.1 Gb
Special Thanks 0mBrE