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Analysis and Design of Networks-on-Chip Under High Process Variation

Analysis and Design of Networks-on-Chip Under High Process Variation
English | Springer | Circuits & Systems | January 16, 2016 | ISBN-10: 3319257641 | 141 pages | pdf | 6.45 mb
by Rabab Ezz-Eldin (Author), Magdy Ali El-Moursy (Author), Hesham F. A. Hamed (Author)
Demonstrates the impact of process variation on Networks-on-Chip of different topologies
Includes an overview of the synchronous clocking scheme, clock distribution network, main building blocks in asynchronous NoC design, handshake protocols, data encoding, asynchronous protocol converters and routing algorithms
Describes a novel adaptive routing algorithm for asynchronous NoC designs, which selects the appropriate output path based on process variation and congestion

From the Back Cover
This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.

Demonstrates the impact of process variation on Networks-on-Chip of different topologies;
Includes an overview of the synchronous clocking scheme, clock distribution network, main building blocks in asynchronous NoC design, handshake protocols, data encoding, asynchronous protocol converters and routing algorithms;
Describes a novel adaptive routing algorithm for asynchronous NoC designs, which selects the appropriate output path based on process variation and congestion.

About the Author
Magdy Ali El-Moursy is an Associate Professor in the Microelectronics Department of the Electronics Research Institute, Cairo, Egypt and Staff Engineer at Design Creation and Synthesis Division of Mentor Graphics Corporation, Cairo, Egypt.

Number of Illustrations and Tables
50 illus., 34 in colour
Topics
Circuits and Systems
Processor Architectures
Electronics and Microelectronics, Instrumentation

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Tags: Analysis, Design, Networks, Process, Variation

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